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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc. 36Mb Pipelined Sync SRAM
FEATURES * Supports bus operation up to 200 MHz * Available speed grades are 200 and 166 MHz * Registered inputs and outputs for pipelined operation * 3.3V core power supply * 2.5V/3.3V I/O power supply * Fast clock-to-output times * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel(R) * Pentium(R) interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * Single Cycle Chip Deselect * Available in lead-free 100-pin TQFP package * IEEE 1149.1 JTAG-Compatible Boundary Scan * "ZZ" Sleep Mode Option OPTION MARKING
/XT /IT /ET Temperature Range Military Temp (-55oC to +125oC) Industrial (-40oC to +85oC) Enhanced (-40oC to +105oC)
AS5SP1M36DQ
SSRAM
FIGURE 1: PIN ASSIGNMENT (Top View)
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AS5SP1M36DQ CY7C1440AV33 (1Mx36)
(1M x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 MODE A A A A A1 A0 NC/72M A VSS VDD
SELECTION GUIDE
200MHz 3.2 425 120 166MH 3.4 375 120
Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current
Unit ns mA mA
GENERAL DESCRIPTION
The AS5SP1M36DQ SRAM integrates 1M x 36/2M x 18 and 512K x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depthexpansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent
AS5SP1M36DQ Rev. 1.2 4/09
burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered onchip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to two or four bytes wide as controlled by the byte write control inputs. GW when active LOW causes all bytes to be written. The AS5SP1M36DQ operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
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A A A A A A A A A
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LOGIC BLOCK DIAGRAM
A0, A1, A
AS5SP1M36DQ
SSRAM
ADDRESS REGISTER
2
A[1:0]
MODE ADV CLK
Q1
ADSC ADSP
BWD DQD ,DQPD BYTE WRITE REGISTER DQC ,DQPC BYTE WRITE REGISTER DQB ,DQPB BYTE WRITE REGISTER DQA ,DQPA BYTE WRITE REGISTER
BURST COUNTER CLR AND Q0 LOGIC
DQD ,DQPD BYTE WRITE DRIVER DQC ,DQPC BYTE WRITE DRIVER DQB ,DQPB BYTE WRITE DRIVER DQA ,DQPA BYTE WRITE DRIVER
BWC
MEMORY ARRAY
SENSE AMPS
OUTPUT REGISTERS
OUTPUT BUFFERS E
BWB
DQs DQPA DQPB DQPC DQPD
BWA BWE
GW CE 1 CE 2 CE 3 OE
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
PIN DEFINITIONS
Name A0, A1, A I/O InputSynchronous InputSynchronous Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3[2]are sampled active. A1: A0 are fed to the two-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK.
BWA, BWC, BWE, BWG, GW
InputSynchronous InputSynchronous InputClock InputSynchronous
Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded.
BWE CLK CE1
AS5SP1M36DQ Rev. 1.2 4/09
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PIN DEFINITIONS (continued)
Name CE2 I/O InputSynchronous InputSynchronous Description
AS5SP1M36DQ
SSRAM
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device. Not available for AJ package version. Not connected for BGA. Where referenced, CE3 is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Power supply inputs to the core of the device. Ground for the core of the device. Ground for the I/O circuitry. Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation. Mode Pin has an internal pull-up. Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages.
CE3
OE
InputAsynchronous
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
ZZ
InputAsynchronous I/OSynchronous
DQs, DQPX
VDD VSS VSSQ VDDQ MODE
Power Supply Ground I/O Ground InputStatic JTAG serial output Synchronous
I/O Power Supply Power supply for the I/O circuitry.
TDO
TDI
JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAGClock - - Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die No Connects. Not internally connected to thedie. NC/72M are address expansion pins & are not internally connected to the die.
TMS
TCK NC NC/72M
AS5SP1M36DQ Rev. 1.2 4/09
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FUNCTIONAL OVERVIEW
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.2ns (200-MHz device). The AS5SP1M36DQ supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486! processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte Write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed Write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the Write signals (GW, BWE) are all deserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.2ns (200-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single Read cycles are supported. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will tri-state immediately.
AS5SP1M36DQ
SSRAM
Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The Write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered Write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the Write operation is controlled by BWE and BWX signals. The AS5SP1M36DQ provides Byte Write capability that is described in the Write Cycle Descriptions table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, will selectively write to only the desired bytes. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because AS5SP1M36DQ is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs.Doing so will tri-state the output drivers. As a safety precaution, DQs are utomatically tri-stated whenever a Write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC Write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the Write inputs (GW, BWE, and BWX) are asserted active to conduct a Write to the desired byte(s). ADSC-triggered Write accesses require a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global Write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a Byte Write is conducted, only the selected bytes are written. Bytes not selected during a Byte Write operation will remain unaltered. A synchronous self-timed Write mechanism has been provided to simplify the Write operations. Because AS5SP1M36DQ is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so will tri-state the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a Write cycle is detected, regardless of the state of OE.
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AS5SP1M36DQ Rev. 1.2 4/09
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FUNCTIONAL OVERVIEW (continued)
Burst Sequences The AS5SP1M36DQ provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both Read and Write burst operations are supported.
AS5SP1M36DQ
SSRAM
Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW.
Interleaved Burst Address Table (MODE=Floating or VDD) First Address A1:A0 00 01 10 11 Second Address A1:A0 01 00 11 10 Third Address A1:A0 10 11 00 01 Fourth Address A1:A0 11 10 01 00
Linear Burst Address Table (MODE=GND) First Second Third Address Address Address A1:A0 A1:A0 A1:A0 00 01 10 01 00 11 10 11 00 11 10 01
Fourth Address A1:A0 11 10 01 00
ZZ Mode Electrical Characteristics Parameter Description IDDZZ Sleep mode standby current tZZS tZZREC tZZI tRZZI Device operation to ZZ ZZ recovery times ZZ active to sleep current ZZ inactive to exit sleep current
Test Conditions ZZ VDD 0.2V ZZ VDD 0.2V ZZ 0.2V This parameter is samples This parameter is samples
Min
Max 2tCYC
Unit mA ns ns ns ns
2tCYC 2tCYC 0
AS5SP1M36DQ Rev. 1.2 4/09
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Truth Table Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Sleep Mode, Power Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst READ Cycle, Continue Burst WRITE Cycle, Continue Burst WRITE Cycle, Continue Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst
[2,3,4,5,6,7]
AS5SP1M36DQ
SSRAM
Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current
CE1\ CE2 CE3\ H X X L L X L X H L L X L X H X X X L H L L H L L H L L H L L H L X X X X X X H X X H X X X X X H X X X X X X X X H X X H X X X X X H X X
ZZ L L L L L H L L L L L L L L L L L L L L L L L
ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK DQ X L X X X L H TRI STATE L X X X X L H TRI STATE L X X X X L H TRI STATE H L X X X L H TRI STATE H L X X X L H TRI STATE X X X X X X TRI STATE Q L X X X L LH L X X X H L H TRI STATE H L X L X LH D Q H L X H L LH H L X H H L H TRI STATE Q H H L H L LH H H L H H L H TRI STATE Q X H L H L LH X H L H H L H TRI STATE H H L L X LH D C H L L X LH D Q H H H H L LH H H H H H L H TRI STATE Q X H H H L LH X H H H H L H TRI STATE H H H L X LH D X H H L X LH D
Notes: 2. X=Don't Care, H=Logic HIGH, L=Logic LOW 3. WRITE\=L when any one or more Byte Write enable signals and BWE\=L or GW\=L. WRITE\=H when all Byte write enable signals, BWE\, GW\=H. 4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not samples with the clock. 5. CE1\, CE2, CE3\ are available only in the TQFP package. BGA package has only 2 chip selects CE1\ and CE2. 6. The SRAM always initiates a read cycle when ADSP\ is asserted, regardless of the state of GW\, BWE\, or BWX\. Writes may occur only on subsequent clocks after the ADSP\ or with the assertion of ADSC\. As a result, OE\ must be driven HIGH prior to the start of the write cycle to allow the outputs to tri state. OE\ is a don't care for the remainder of the write cycles. 7. OE\ is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri state when OE\ is inactive or when the device is deselected, and all data bits behave as output when OE\ is active (LOW).
Truth Table for Read/Write [4, 8, 9] Function Read Read Write Byte A (DQA and DQPA) Write Byte B (DQB and DQPB) Write Bytes B, A Write Byte C (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D (DQD and DQPD) Write Bytes D, A Write Bytes D,B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes
GW\ H H H H H H H H H H H H H H H H H L
BWE\ H L L L L L L L L L L L L L L L L X
BWD\ X H H H H H H H H L L L L L L L L X
BWC\ X H H H H L L L L H H H H L L L L X
BWB\ X H H L L H H L L H H L L H H L L X
BWA\ X H L H L H L H L H L H L H L H L X
Notes: 8. BWX\ represents any byte write signal. To enable any byte write BWX\, a Logic LOW signal should be applied at clock rise. Any number of byte writes can be enabled at the same time for any given write. 9. Table only lists a partial listing of the byte write combinations. Any combination of BWX\ is valid. Appropriate write will be done based on which byte write is active.
AS5SP1M36DQ Rev. 1.2 4/09
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The AS5SP1M36DQ incorporates a serial boundary scan test access port (TAP). This part is fully compliant with IEEE Standard 1149.1. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The AS5SP1M36DQ contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device.
AS5SP1M36DQ
SSRAM
Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
Test MODE SELECT (TMS) The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.)
TAP Controller State Diagram g
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 0 1 0 1
TAP Controller Block Diagram
0 Bypass Register
210
TDI
1 UPDATE-IR 1 0
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitr y
TDO
Identification Register
x. . . . .210
Boundary Scan Register
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
TCK TMS TAP CONTROLLER
Note: The JTAG feature is not tested. GBNT.
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Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
AS5SP1M36DQ
SSRAM
during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state.
Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path.
IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM.
The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the CaptureDR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO pins when the TAP controller is in a Shift-DR state. The SAMPLE Z command puts the output bus into a High-Z state until the next command is given during the "Update IR" state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE/PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be
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Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code
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possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required--that is, while data captured is shifted out, the preloaded data can be shifted in.
AS5SP1M36DQ
SSRAM
alsoselects the boundary scan register to be connected for serial access between the TDI and TDO in the shift-DR controller state.
EXTEST OUTPUT BUS TRI-STATE IEEE Standard 1149.1 mandates that the TAP controller be able to put the output bus into a tri-state mode.
The boundary scan register has a special bit located at, bit #89 (for 165-FBGA package) or bit #138 (for 209-FBGA package). When this scan cell, called the "extest output bus tri-state", is latched into the preload register during the "Update-DR" state in the TAP controller, it will directly control the state of the output (Q-bus) pins, when the EXTEST is entered as the current instruction. When HIGH, it will enable the output buffers to drive the output bus. When LOW, this bit will place the output bus into a High-Z condition. This bit can be set by entering the SAMPLE/PRELOAD or EXTEST command, and then shifting the desired bit into that cell, during the "Shift-DR" state. During "Update-DR", the value loaded into that shift-register cell will latch into the preload register. When the EXTEST instruction is entered, this bit will directly control the output Q-bus pins. Note that this bit is pre-set HIGH to enable the output when the device is powered-up, and also when the TAP controller is in the "Test-Logic-Reset" state.
BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO pins. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. EXTEST The EXTEST instruction enables the preloaded data to be driven out through the system output pins. This instruction
Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
Tap Timing
1 Test Clock (TCK)
t TMSS
2
3
4
5
6
t TH t TMSH
t
TL
t CYC
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
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TAP AC Switching Characteristics Over the operating range Parameter Description Clock tTCYC TCK Clock Cycle Time tTF tTH tTL TCK Clock Frequency TCK Clock HIGH Time 20 20 10 0 5 5 5 5 5 5 Min 50 20
[10,11]
AS5SP1M36DQ
SSRAM
Max
Unit ns MHz ns ns ns ns ns ns ns ns ns ns
TCK Clock LOW Time Output Times tTDOV TCK Clock LOW to TDO Valid tTDOX TCK Clock LOW to TDO Invalid Set up Times tTMSS TMS Set up to TCK Clock Rise tTDIS tCS TDI Set up to TCK Clock Rise Capture Set upo to TCK Rise
Hold Times tTMSH TMS Hold after TCK Clock Rise tTDIH tCH TDI Hold after Clock Rise Capture Hold after Clock Rise
3.3V TAP AC Test Conditions
Input pulse levels....................................Vss to 3.3V Input rise and fall times.......................................1ns Input timing reference levels...............................1.5V Output reference levels......................................1.5V Test load termination supply voltage ...................1.5V
2.5 TAP AC Test Conditions
Input pulse levels....................................Vss to 2.5V Input rise and fall times.......................................1ns Input timing reference levels..............................1.25V Output reference levels.....................................1.25V Test load termination supply voltage .................1.25V
3.3V TAP AC Output Load Equivalent
1.5V 50 TDO ZO = 50 20pF
2.5 TAP AC Output Load Equivalent
1.25V 50 TDO ZO = 50 20pF
Notes: 10. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register. 11. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
TAO DC Electrical Characteristics and Operating Conditons 0oCAS5SP1M36DQ
SSRAM
Max
Unit V V V V
Output HIGH Voltage IOH= 100A Output LOW Voltage IOL=8.0mA IOL=1.0mA
0.4 0.4 0.2 0.2 VDD+0.3 VDD+0.3 0.8 0.7 5
V V V V V V V V A
Output LOW Voltage IOH=100A Input HIGH Voltage Input LOW Voltage Input Load Current
Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) [13] Architecture / Memory Type (23:18) Bus Width / Density (17:12) JEDEC ID Code (11:1) + ID Register Presence Indicator (0) 1M x 36 000 01011 000000 100111 00000110100 1 Description Describes the version number Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor Indicates the presence of an ID register
Scan Register Sizes Register Name Instruction Bypass ID Bit Size (x36) 3 1 32
Notes: 12. All voltages referenced to VSS (GND). 13. Bit #24 is '1' in the ID Register Definitions for both 2.5V and 3.3V versions of this device.
+
Austin Semiconductor uses Cypress die so this code reflects Cypress.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111
AS5SP1M36DQ
SSRAM
Description Captures the I/O ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High Z state. Do not use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do not use: This instruction is reserved for future use. Do not use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................-65C to +150C Ambient Temperature with Power Applied..................................................-55C to +125C Supply Voltage on VDD Relative to GND.......... -0.3V to +4.6V Supply Voltage on VDDQ Relative to GND ........ -0.3V to +VDD DC Voltage Applied to Outputs in Tri-State.................................................. -0.5V to VDDQ + 0.5V DC Input Voltage ........................................ -0.5V to VDD + 0.5V Current into Outputs (LOW)............................................. 20 mA Static Discharge Voltage............................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current........................................................... > 200 mA
Operating Range Ambient Temperature 0oC to +70oC 40oC to +85oC 40oC to +105oC 55oC to +125oC
Range Commercial Industrial Enhanced Military
VDD
VDDQ
3.3V 5%/+10%
2.5V 5% to VDD
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Electrical Characteristics Over the Operating Range [17, 18] DC Electrical Characteristics Over the Operating Range Parameter Description VDD Power Supply Voltage VDDQ VOH VOL VIH VIL I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage [17] Input LOW Voltage [17] Input Leakage Current except ZZ and MODE IX Input Current of MODE Input Current of ZZ Ioz IDD Output Leak Current VDD Operating Supply Current Automatic CE Power Down TTL Inputs Automatic CE Power Down CMOS Inputs Automatic CE Power Down CMOS Inputs Automatic CE Power Down TTL Inputs for 3.3V I/O for 2.5V I/O for 3.3V I/O, IOH= 4.0mA for 2.5V I/O, IOH= 1.0ma for 3.3V I/O, IOH=8.0mA for 2.5V I/O, IOH=1.0ma for 3.3V I/O for 2.5V I/O for 3.3V I/O for 2.5V I/O GND V1 VDDQ Input = VSS Input = VDD Input = VSS Input = VDD GND V1 VDDQ, Output Disabled VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected Current VIN VIH or VIN VIL f = fMAX = 1/tCYC VDD = Max, Device Deselected Current VIN 0.3V or VIN VDDQ 0.3V, f=0 VDD = Max, Device Deselected Current VIN 0.3V or VIN VDDQ 0.3V, f = fMAX = 1/tCYC VDD = Max, Device Deselected Current VIN VIH or VIN VIL, f = 0 All Speeds All Speeds All Speeds 5 ns cycle, 200 MHz 6 ns cycle, 167 MHz 5 5 2.0 1.7 0.3 0.3 5 30
AS5SP1M36DQ
SSRAM
Test Conditions
Min 3.135 3.135 2.375 2.4 2.0
Max 3.6 VDD 2.625
Unit V V V V V V V V V V V A A A A A A mA mA mA
0.4 0.4 VDD+0.3V VDD+0.3V 0.8 0.7 5
5 30 5 425 375 225
ISB1
ISB2
120
mA
ISB3
All Speeds
200
mA
ISB4
135
mA
Notes: 17. Overshoot: VIH (AC) < VDD +1.5V (Pulse width less than TCYC/2), undershoot: VIL (AC) > 2V (Pulse width less than tCYC/2) 18. Tpower up: Assumes a linear ramp from 0V to VDD (min) within 200ms. During this time VIH < VDD and VDDQ VDD.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Capacitance [19] 100 TQFP Max. 6.5 3 5.5
AS5SP1M36DQ
SSRAM
Parameter CIN CCLK CI/O
Description Input Capacitance Clock Input Capacitance Input/Output Capacitance
Test Conditions TA = 25oC, f=1MHz, VDD = 3.3V VDDQ = 2.5V
Unit pF pF pF
Thermal Resistance [19] 100 TQFP Package 25.21 2.28
Parameter JA JC
Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case)
Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51
Unit
o
C/W C/W
o
AC Test Loads and Waveforms
3.3V I/O Test Load
OUTPUT Z0 = 50 RL = 50 5 pF INCLUDING JIG AND SCOPE R = 351 3.3V OUTPUT
R = 317 ALL INPUT PULSES VDDQ 10% GND 1ns 90% 90% 10% 1ns
VT = 1.5V (a)
(b)
R = 1667 VDDQ 10% GND R = 1538 1ns
(c)
2.5V I/O Test Load
OUTPUT Z0 = 50 RL = 50 VT = 1.25V 5 pF INCLUDING JIG AND SCOPE 2.5V OUTPUT ALL INPUT PULSES 90% 90% 10% 1ns
(a)
(b)
(c)
Note: 19. Tested initially and after any design or process change that may affect these parameters.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Switching Characteristics Over the Operating Range
[24, 25]
AS5SP1M36DQ
SSRAM
200 Parameter tPOWER Clock tCYC tCH Description [20] [20] VDD (Typical) to the first access Clock Cycle Time Clock HIGH Min 1 5 2.0 2.0 3.2 1.5 1.3 3.0 3.0 0 3.0 1.4 1.4 1.4 1.4 1.4 1.4 0.4 0.4 0.4 0.4 0.4 0.4 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 0 1.5 1.5 Max Min 1 6 2.4 2.4
166 Max Unit ms ns ns ns 3.4 ns ns ns 3.4 3.4 3.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tCL Clock LOW Output Times tCO Data Output Valid After CLK Rise tDOH tCLZ tCHZ tOEV tOELZ Data Output Hold After CLK Rise Clock to Low Z [21, 22, 23] Clock to High Z
[21, 22, 23]
OE\ LOW to Output Valid OE\ LOW to Output Low Z [21, 22, 23]
[21, 22, 23]
OE\ HIGHto Output Low Z tOEHZ Set Up Times tAS Address Set up Before CLK Rise tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH ADV\ Set up Before CLK Rise
ADSC\, ADSP\ Set up Before CLK Rise GW\, BWE\ BWx\ Set up Before CLK Rise Data Input Set up Before CLK Rise Chip Enable Set up Before CLK Rise Address Hold After CLK Rise ADSP\, ADSC\ Hold After CLK Rise ADV\ Hold After CLK Rise GW\, BWE\ BWx\ Set up After CLK Rise Data Input Set up After CLK Rise Chip Enable Set up After CLK Rise
Notes: 20. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 21. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured 200 mV from steady state voltage. 22. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High Z prior to Low Z under the same system conditions. 23. This parameter is sampled and not 100% tested. 24. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 25. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Switching Waveforms
Read Cycle Timing[26]
t CYC
AS5SP1M36DQ
SSRAM
CLK t CH t CL
t
ADS
t ADH
ADSP t ADS ADSC t AS tAH tADH
ADDRESS
A1 t WES tWEH
A2
A3 Burst continued with new base address
GW, BWE, BWx t CES tCEH CE t ADVS tADVH ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z t CO Burst wraps around to its initial state Single READ BURST READ Q(A1) t OELZ t CO t DOH Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) t CHZ Q(A2 + 1) Deselect cycle
DON'T CARE
UNDEFINED
Note: 26. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Switching Waveforms (continued)
Write Cycle Timing[26, 27]
t CYC
AS5SP1M36DQ
SSRAM
CLK t CH t ADS ADSP ADSC extends burst tADH t ADS tADH tADH t CL
t ADS ADSC t AS tAH
ADDRESS
A1 Byte write signals are ignored for first cycle when ADSP initiates burst
A2
A3
t WES tWEH
BWE, BWX t WES tWEH GW t CES tCEH CE t t ADVS ADVH ADV ADV suspends burst
OE t DS
tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note: 27. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Switching Waveforms (continued)
Read/Write Cycle Timing[26, 28, 29]
t CYC
AS5SP1M36DQ
SSRAM
CLK t CH t ADS ADSP tADH t CL
ADSC t AS tAH
ADDRESS
A1
A2
A3 t WES tWEH
A4
A5
A6
BWE, BWX t CES tCEH CE
ADV
OE tCO t DS t DH t OELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ D(A3) D(A5) D(A6)
Q(A2) Single WRITE
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes: 28. The data bus (Q) remains in high-Z following a Write cycle, unless a new read access is initiated by ADSP or ADSC. 29. GW is HIGH.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Switching Waveforms (continued)
ZZ Mode Timing[30, 31]
CLK
t ZZ t ZZREC
AS5SP1M36DQ
SSRAM
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes: 30. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 31. DQs are in high-Z when exiting ZZ sleep mode.
AS5SP1M36DQ Rev. 1.2 4/09
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
Package Diagrams
100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)
16.000.20 14.000.10
100 1 81 80
AS5SP1M36DQ
SSRAM
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
AS5SP1M36DQ Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
20
0.10
R 0.08 MIN. 0.20 MAX.
AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
ORDERING INFORMATION
Part Number Configuration o o Industrial ( 40 C to +85 C) AS5SP1M36DQ 167/IT 1M x 36 Pipelined Synch SRAM AS5SP1M36DQ 200/IT 1M x 36 Pipelined Synch SRAM o o Enhanced ( 40 C to +105 C) AS5SP1M36DQ 167/ET 1M x 36 Pipelined Synch SRAM AS5SP1M36DQ 200/ET 1M x 36 Pipelined Synch SRAM o o Military Temp ( 55 C to +125 C) AS5SP1M36DQ 167/XT 1M x 36 Pipelined Synch SRAM AS5SP1M36DQ 200/XT 1M x 36 Pipelined Synch SRAM PB OPTION (WHERE AVAILABLE) Part Number Configuration o o Industrial ( 40 C to +85 C) AS5SP1M36DQR 167/IT 1M x 36 Pipelined Synch SRAM AS5SP1M36DQR 200/IT 1M x 36 Pipelined Synch SRAM o o Enhanced ( 40 C to +105 C) AS5SP1M36DQR 167/ET 1M x 36 Pipelined Synch SRAM AS5SP1M36DQR 200/ET 1M x 36 Pipelined Synch SRAM o o Military Temp ( 55 C to +125 C) AS5SP1M36DQR 167/XT 1M x 36 Pipelined Synch SRAM AS5SP1M36DQR 200/XT 1M x 36 Pipelined Synch SRAM Speed (MHz) 167 200 167 200 167 200 Speed (MHz) 167 200 167 200 167 200
AS5SP1M36DQ
SSRAM
Pkg. 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP
Pkg. 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP 100 Pin TQFP
Temperature Range Military Temp (-55oC to +125oC) Industrial (-40oC to +85oC) Enhanced (-40oC to +105oC)
AS5SP1M36DQ Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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AUSTIN SEMICONDUCTOR, INC. Austin Semiconductor, Inc.
DOCUMENT TITLE
AS5SP1M36DQ
SSRAM
36Mb Pipelined Sync SRAM
REVISION HISTORY Rev # 1.0 1.1 1.2
+
History Datasheet Creation+ updated order chart updated speeds (pg1, 15)
Release Date January 2009 March 2009 April 2009
Status Release Release Release
From baseline Cypress datasheet doc# 38-05383 Rev E
AS5SP1M36DQ Rev. 1.2 4/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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